DS vs DS Mk II

Hi Ted, I’m wondering about the I2S input of the Mk II. Is it only accepting the PSA ‘standard’, or is it adaptable to other standards, including perhaps proprietary ones like from Auralic? Thanks.

It assumes that the physical wires are hooked up like HDMI, e.g. 4 sets of differential high speed twisted pairs, etc.

What those four bits mean is up to the FPGA software. There should be an interface for picking the polarity of each of the three important signals and picking which channel is which in DSD. I’m not sure if that will be in the first beta software release or not.

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Interesting! I’m looking forward to hearing your findings/thoughts in further development of what may be a great feature. Although I can think of commercial caveats as well.

Hi Ted,

Regarding the FPGA in the MKII (Artix 7):

  • are you still using semi parallel filtering in the MKII?
  • is your aim to use as many slices as possible in parallel to reduce processing times and thus potential jitter?
  • has your FIR coding changed significantly in the MKII? Or is it just the coefficients (accuracy)?

Thanks

Tho often in an FPGA pipelining is the key to performance, for a tight filter doing the channels in parallel can simplify all of the coefficient bookkeeping and handling of intermediate values. Both the DS and the DS Mk II (and TSS for that matter) do the channels in parallel for both upsampling and in the sigma delta converter (tho the volume is pipelined in the middle :slight_smile: )

Jitter and noise are reduced in the FPGA by doing work in as even of chunks everywhere as possible. This is most effectively done by using parallel sometimes, serial sometimes, ad hoc, … which ever works best in a unit of code. The thing to avoid is one parallel section finishing at a different time than other related parallel tasks. Or to avoid things like two active pipeline steps followed by an empty step…

All of the filtering was recoded from scratch for the Mk II. The overall architecture of each upsampling filter has been the same. In general, four parallel multiply/accumulates per channel with a final summing of the four streams in each sample after all of the coefficients are processed. Since the FPGAs have dual port memory, I can read the coefficients forwards and backwards at the same time so the first quarter and last quarter of the multiplies are done in parallel using the first quarter of the coefficients and the middle half uses the second quarter of the coefficients. Thereby only storing one half of the coefficients.

Each multiply of the eight in parallel on the Spartan 6 was done with three hardware DSP units. On the Spartan 7 only two DSPs are needed per multiply.

The Mk II upsamples PCM to 705.6k where the DS upsampled to 352.8k so there are twice as many multiplies per unit time on the Mk II. I also use wider coefficients on the Mk II and more taps in the filters.

Finally in the DS I found that deleting the final filter for upsampling 48, 96 and 192 to 20 x the DSD rate made things sound better at the expense of a little more noise at 352.8k (which tho not audible, it doesn’t look great on some measurements.) On the Mk II there are two new upsampling filters running in parallel with the original filter for processing 48, 96 and 192k. They have squirrelly up to down ratios and do the math in a different order to save on overall processing and allow the processing to run at a lower rate than a direct 768k to 20 x the DSD rate followed by a decimation of 5.

It was fun redoing all of the FIR filters on the Spartan 7. The 7 series of FPGAs have DSP units directly designed to do wide multiply/accumulates for FIR filtering and they work well. I did spend a lot of time simulating the filters and checking the results with high precision math in Maxima and Matlab.

I also coded up a couple of triple precision IIR filters, but I didn’t use them in the end.

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Ted,

Do you know what the output voltage will be for the DS Mk II over XLR?

The reason I ask is that my integrated amp will stay in Class A if it receives a high enough output voltage signal.

Thanks

XLR will be 4VRMS and RCA can be selected to be either 2VRMS or 4VRMS.

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Thanks!

Ted, I just came upon this thread ( I feel like an idiot for not seeing it sooner ). Will take me at least a week or two to devour it. All I can say right now is it looks incredible! :+1:

Hi @Ted,

I really liked your functional way of explanation the last time on the FPGA/FIR. As such, could you explain a bit on the essential analogue circuits (excluding the power tree) in the MKII including:

  • The low Pass Filter (e.g. is it still a RC filter and does it use the same filter algorithm?)
  • The opamp circuit (e.g. what does this bit buffering actually mean?)
  • Are there any other analogue circuits worth mentioning impacting sound quite a bit?

Thanks

The original design of my prototype was an RCLRC filter where the L was the leakage inductance of the transformer. With the DS the transformers was less well known to me so I added filtering in the digital switches (video opamps.) The DS Mk II and TSS go back to the bare digital switches (opamp with gain only) and an RCLRC passive filter. Also with the DS Mk II and TSS we know that the output from the FPGA is quad rate so the passive filter has a larger frequency range to filter over. (i.e. can be a less steep filter, have a higher -3dB point or some combination of both.)

What I called the digital switches are really a video opamp. Its job is to connect the output to one power rail for an incoming digital one and to the other power rail for an incoming digital zero. I the DS I also used them for the first stages of filtering, so they were used a little more like most people use opamps. One might think of the opamps as providing a lower impedance output of its input (the definition of a buffer) but actually the input to the opamps (the output of the reclocker) is approx 200 ohms and the output of the opamps is set to 175 ohms at a higher voltage so the opamps aren’t really a buffer at all.

Well, beside the digital switches and the passive output filtering (including the output transformer) there isn’t any traditional analog circuitry at all. But the reclockers and the master clock affect the output directly and have to have good power supplies and careful routing, etc. so one might consider them analog circuitry as well.

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So the quality of the transformers seem to have quite an impac?

Yes the qualities of the transformers matter in multiple ways,

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Could you expand on this a little, please Ted? How does the opamp contribute to filtering – is it because they have limited bandwidth themselves or something to do with the surrounding circuit or…?

In the DS I explicitly configured the opamps as two pole MFB filters using caps in the feedback loop and on the inputs. I was worried that the Edcor transformers wouldn’t have the filter shape I needed. In my original prototype, the DS Jr, DS Mk II and TSS I just use the opamp for gain and slew rate limiting.

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So it would seem that it is better to keep the filter polls after the video op amps, rather that around the feedback loop or at the input. Could you please elaborate on why that is?
Thanks.

One obvious difference is active vs. passive filtering. But I’m not an ideologue on that account. Keeping higher frequencies away from the output transformer might make a difference, it may not be as linear at frequencies much higher than it was designed for, but that doesn’t seem to be a problem either. I originally chose an opamp that would be slew rate limiting in this application assuming it would be more consistent when slew rate limiting than the external transmission lines. I don’t think this turned out to be a problem in practice. Another practical difference is what parts of the output circuits need to handle higher voltages, if the opamp is also filtering, the outputs of the opamp and the transformer won’t be subject to as high voltages.

All in all I think the differences are just balancing of tertiary effects.

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7 posts were merged into an existing topic: Modding the DirectStream DAC

Hi @Ted,

I like capacitors as they don’t cause voltage drops and can reduce ripple and HF noise if applied correctly…

I was wondering in the MKII: will there be caps at all in the signal path? And on how many levels in the power tree did you apply caps (right after the diodes > global caps > local caps > caps on opamp circuit > LPF)

Thanks

“In the signal path” isn’t a well defined term. There is no capacitor audio coupling in the DS (and there is transformer coupling :slight_smile: ). Conversely everything is in the audio path in that everything can have as big a difference in the output as a cap choice.

Most regulators in the DS Mk II have a RLC filter in front of them, but the L significant only at high frequencies. The C is in the expected place between the power and ground. They all also have caps on their outputs. The power supply isn’t the normal diodes-caps-regulator style power supply. Still there are 11 caps between the diodes and the first regulator. There are another 5 caps in that regulator for various purposes. For the analog outputs there’s another RLC-regulator-Cs, Then another RLC-Regulator-Cs for each channel. Then 6 caps on the power of each of the four opamps per channel. After that there are two audio RC filters, the transformer and a CR filter. There are replications of the RLC-regulator-Cs for each of the clock, the clock control, the 2nd reclocker, the other CMOS, the relays… Also there are plenty of bypass caps on the power for virtually every chip. The voltage drops in the RLC’s is designed in and has no negative effects and definitely positive effects.

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