Out of curiosity, how many lines of code are they up to in the DS firmware?
And what percentage of the gates in the FPGA are still available?
It’s hard to answer directly: I have multiple implementations of various pieces I pick between depending on my needs. Also the Xilinx tools can produce code from specs and that code isn’t dense at all.
The modules currently in the FPGA comprise about 5000 lines that I wrote and then there are things like FIFOs and FIR filters generated by the Xilinx tools from specs and coefficients I provide (the coefficients in one case were generated by a small program in my HP-48 calculator )
I don’t know if you were only asking about the FPGA but the PIC in the control processor is in C and has a lot of generated code too. Also the XMOS code for USB is non-trivial, but mostly not written by us. Then there’s the bridge…
FPGAs these days are much more than just a sea of gates – there are specialized resources like clock PLLs, blocks of RAM, DSP blocks, etc. With different compile options you can choose to slosh, say, a multiplier to use mostly DSP blocks or mostly simple gates and similarly for hunks of memory. One of the previous releases used about 140% of the FPGA but with optimizations got squeezed to 98% of the FPGA. Conversely another version uses about 80% of the gates and has a lot of memory and DSP blocks left over.
I have a lot of parameters I can tweak in the source to balance speed vs. size, etc. and when I need more of one or the other the FPGA resource balance changes wildly.
There is room for a few more non-trivial features and if needed there are a few things that I can get rid of that aren’t being used at the moment.
(I assume you weren’t asking about unit testing harnesses, etc. which is another whole hunk of code.)