It’s still within 10xDSD 
Alekz said It's still within 10xDSDI saw the smiley, but I'll take it literally anyway. 4 x DSD doesn't divide 10 x DSD evenly
There’s a point of diminishing returns for sample rates since the jitter effects go up with higher rates - somewhere around 2 x DSD and 4 x DSD is the sweet spot. Somewhere up there it’s just a numbers game.
Still it is possible to do DSD256 in the DS with more FPGA software, but the more software the harder to keep the jitter out.
Not all that long ago, this was the argument against higher rate PCM; timing inaccuracies overwhelms any advantage of sampling rates of higher than, e.g., 96kHz. At that time the limitation was the hardware.
Is this now the case with higher rate DSD? What is the limitation? Is it clocks, buffers, etc. or is it more a practical limitation akin to thermal noise when attempting to obtain S/N better than 120dB?
It is still the hardware. Remember, at the time we launched the Bridge, few people were able to stream 192kHz, most hardware was restricted to 96kHz. 192kHz was a revelation at the time. So, drivers and hardware.
Elk said Not all that long ago, this was the argument against higher rate PCM; timing inaccuracies overwhelms any advantage of sampling rates of higher than, e.g., 96kHz. At that time the limitation was the hardware.Is this now the case with higher rate DSD? What is the limitation? Is it clocks, buffers, etc. or is it more a practical limitation akin to thermal noise when attempting to obtain S/N better than 120dB?
It’s fundamental, the higher the sample rate the more a given jitter affects the output. For single bit sigma delta the rule is fairly simple: doubling the sample rate doubles the jitter contribution to the audio band. The details are more complicated for multibit sigma delta but the sweet spot is still around 2 or 4 time DSD rate. At some point raising the sample rate still raises the resultant noise from jitter more than it lowers the noise from more accurate sampling.
Thanks!