@tedsmith
Thanks.
I suspect there is more going on since Bridge-2 is in design.
Otherwise It could be just a simple network card and adapted by firmware? Leyman’s guess.
G
@gordon
If only bridges were simple 
My only point was that the DAC doesn’t care how the bridge works, just that bits come. The bridge needs lots of buffering so it can deal with late messages, message retry, etc. let alone all of the transcoding and DLNA/UPnP issues.
@tedsmith
Thanks.
Ted how would compare the Sound of your EMM Dac and the DirectStream is the difference obvious. I ask because I believe Eds Meitners stuff is among the best out there.
Thanks for chatting with us
To PS Audio Ted
Has the directstream got upgradable firmware? and is the existing bridge firmware compatible? or is new firmware required, if I was to slot my existing bridge into the Directstream unit?
@magicknow
I too find the DAC6e among the best out there and have been happy with it for years.
The DirectStream and the EMM DAC6e are similar sounding (they both convert all inputs to double rate DSD.) Tho with a quick A/B I personally don’t hear gobs of differences, for longer term listening I definitely prefer the DirectStream. It’s more engaging and I find I listen to more music with it. When my daughter was pregnant she had hypersensitive hearing for a while. When I asked her to do a blind A/B between them every time I selected the DAC6e she said “Stop That!”
@johno@datacom.co.nz
The existing bridge works in the DirectStream just as it does in the PWD. The DirectStream doesn’t use it any differently that the PWD. (It just sees the bridge as another I2S input.)
The DirectStream has updatable firmware in the PIC (like the PWD), the bridge (like the PWD), the graphics for the display (like the PWD) and in the DirectStream digital card’s FPGA and also the DirectStream digital card’s XMOS USB processor.
The XMOS USB firmware is fairly static.
I make no promises but I seem to keep finding ways to shoehorn in new features or (more rarely) enhancements to the sound into the FPGA firmware. The reason I’m using an FPGA is because I’m a software guy and that way I don’t have to keep changing hardware
The upgrade replaces all three boards and the transformer inside, so unfortunately it's the majority of what's in the PWD itself. All that remains is the chassis and the front panel display. Upgrades will cost $2995. Or, you can get $2K trade in for the PWD and get a brand new DirectStream for $3995.
Hello would this kind of trade work outside of US (France for example) ?
BR
The upgrade replaces all three boards and the transformer inside, so unfortunately it's the majority of what's in the PWD itself. All that remains is the chassis and the front panel display. Upgrades will cost $2995. Or, you can get $2K trade in for the PWD and get a brand new DirectStream for $3995.
Paul,
Will upgrading one's existing PWD be a kit to be sent to the owner for them to replace the boards and transformer themselves or will the owner send it to PS Audio to do the work?
Thanks
Holy Crap! I am a slow reader and I just got done reading a number of interesting threads here, including this one. Regardless of how well the DirectStream DAC works, the way it works is amazing. Some of the ways that things are done seem strange at first but make sense on further examination. Now… If it only sounds as good as it looks.
Still, I wonder about several things.
Why is the DAC running at Double DSD and not 4, 5 or even 10x since the data rate is that high internally?
Is the volume control really only passing 20 bits? Why not a few more, just because? And: is 49.5dB attenuation really enough to allow for full volume control range when accounting for system matching, even counting the selectable output level?
Speaking of selectable output level, what are the choices?
Makes me wish I wasn’t broke at this time. I hope that the upgrade kit availability is not too short lived.
J.P.
@wingsounds13
Howdy
There are tradeoffs for various output sample rates:
Single rate DSD doesn’t leave enough room for the passive low pass filter we want to use, it also forces the noise shaping noise closer to 20kHz than we’d like. On the other hand it has the lowest sensitivity to jitter.
Double rate DSD gives us all the room we want to passively filter the bit stream and to have a flatter “DSD” hump in the 60kHz region. But it’s jitter sensitivity is double that of single rate DSD.
As you go higher the jitter sensitivity for single bit DSD converters goes up linearly: not good news for higher rates. Even for multibit sigma delta dacs the sweet spot is around double rate DSD.
Going much higher for the VCXO frequency would also cause more jitter.
Higher output frequencies require faster switching (steeper edges) to avoid too much THD. Having clean repeatable edges is key to a good signal to noise ratio.
Going higher than double rate gains nothing (the help on the output filter isn’t needed) and can loose a lot.
The PS Audio PWD has a 100 step, 1/2 dB per step volume control. Using 20 bits at the FPGA represents the 100 steps with no more than about 0.03% error. Looking at it another way 20 bits is 120dB of range. Why would anyone need more? The actual UI range and the mapping from the UI range to the FPGA range is done in the UI code and if more range is needed it’s a simple UI change. If a 20 bit volume range ever turns out to be too few bits it’s only an FPGA “recompile” to get more. Perhaps you were thinking of the total resolution of the volume control which is the complete 50 bit product of the 20 bit volume control and the 30 bit high rate signal: we don’t drop any bits on the floor as we convert to single bit double rate DSD.
In addition there is a selectable analog 20dB attenuator for higher sensitivity systems.
-Ted
Oh, thanks. Yes, I was thinking you were passing 20 bits to the PCM>PDM converter. Makes more sense your way. I do get that PDM has its greatest resolution at low signal levels, so reducing the level going into a true 1 bit DAC has essentially no loss at low levels.
Thanks for the education on sample rates. All of that makes sense. As for the jitter sensitivity I vaguely remember reading something like that before but had forgotten it. That would be a fundamental that you would not forget it you are living in that world.
J.P.
frode said: but in DSD plus (DoP) there is, at least for the Wolfson DAC's.
Isn't it done in the PCM domain as well? When I checked the Wolfson chips I noticed that they have internal DSD->PCM conversion.
Yes, it is done on the chip after PCM conversion.
I am interested if there is a early bird discount on the loyal customers
tedsmith said: The reason I'm using an FPGA is because I'm a software guy and that way I don't have to keep changing hardware
Goood! ;)
tedsmith said: The master clock signal is ignored (we don't sync to the incoming clocks, we just sample them, so the master clock is irrelevant).
Conceptually, this makes a great deal of sense. Very cool.
To be honest I still do not understand how it helps to eliminate jitter, especially if the Lens if removed. I do understand how it can be done by a memory buffer aka Lens aka NativeX and by timers. Something like computer serial asynchronous connections (but jitter is pretty much irrelevant there).
tedsmith said: Perhaps you were thinking of the total resolution of the volume control which is the complete 50 bit product of the 20 bit volume control and the 30 bit high rate signal: we don't drop any bits on the floor as we convert to single bit double rate DSD.
This is the confirmation I wanted to hear! 30+20!
To be honest I still do not understand how it helps to eliminate jitter, especially if the Lens if removed. I do understand how it can be done by a memory buffer aka Lens aka NativeX and by timers. Something like computer serial asynchronous connections (but jitter is pretty much irrelevant there).
The way I read it, the DS just ignores the incoming clock from all inputs. If there is no clock there is no jitter, just data. The data is then buffered internally in the FIFO and then released as 2x DSD with the VXCO dictating the rate of release. As long as the data is correctly ordered, it's jitter is that of the VXCO clock. It will be interesting to hear if cables, transports and servers truly no longer matter.
To me, the biggest unanswered question is how the PCM data gets converted to PWM (DSD), as this is the step that Paul is hyping up as "revolutionary", and a way of rediscovering PCM. I suspect this is where the proprietary FPGA does its hardest work and is most sensitive to programming changes.
Still no answer if international customers can access the trade-in option...?
stereophilus said: As long as the data is correctly ordered, it's jitter is that of the VXCO clock. It will be interesting to hear if cables, transports and servers truly no longer matter.
Oh, indeed. Now it's more clear. I also have just watched the three Ted's videos where he talks about jitter. But I think they are to be continued.
Does this now make the bridge obsolete. Or at least considerably reduce the need for it?