The point that people have been trying to make is that with the DS the separation of the clocks is completely immaterial - the clocks aren’t used in the DS and the DS only looks at the steady state values of the data. All digital inputs (whether I2S or AES, etc.) are sampled at 169.344MHz - then pattern matching is performed to see what the data is. The master clock for I2S isn’t hooked up at all and the I2S bit clock is just part of the pattern matching, no edges are ever looked at nor timed.
We’re not denying that you hear what you hear, we are just saying that your technical descriptions of what is happening are not correct in this circumstance.