I’m considering the DS given its logical simplicity and obviously very positive reviews. I’ve been trying to piece together bits of information from this forum, other forums, and PSA videos etc. about the DS. There has been a lot of speculating that an input DSD signal is being somehow “degraded by being converted to PCM first” (rather than some kind of “pure DSD passthrough”) before being put out at 2xDSD.
I don’t believe this is the case (that the upsampling in any way “degrades” the DSD signal) and want to see if I have this roughly right. I apologize if this was clearly explained somewhere else.
To upsample PCM/DSD you essentially:
(1) add least significant bits to the signal (up to a total of 30 or 50?)
(2) duplicate data (or fill 0s) “in time”.
Thus there is no effective mathematical change to either a PCM or DSD signal: the signal is being multiplied by an integer factor in amplitude and being stretched by an integer factor in time. Keeping everything integer means the PCM or DSD signal is perfectly represented for any current sampling rate and bit depth (e.g. 1-bit DSD, or 16/24-bit PCM). Do I have this right so far?
Then you do (delta sigma?) magic to convert a PCM to DSD, downsample and reclock it on the way out and the LRC filter does it’s thing. Thus a DSD input signal isn’t really being converted to PCM in the traditional sense but simply scaled in amplitude and time to be a perfect multiple of the original. By construction there is no loss of information for DSD (or 2xDSD) input. Thus there is no difference between a theoretical “pure DSD passthrough” and what you are doing, since you’d probably buffer anyway (to remove jitter) and the signal ends up being the same. Is this correct?
Also, since everything is buffered, as long as the input signal from any input channel (coax, optical, USB) is bit-wise identical there is no effect on sound quality due to input type. This is what I would hope for any digital device (ignoring jitter), but perhaps the DS is one of the few that ensures this by design (by removing jitter from the source data).
Is this at all in the ballpark?
(I also have a few questions about FPGA but want to see if I’m starting from the right understanding of the basic process.)