Talking about noise floor, especially a 350dB noise floor in digital algo’s is probably more confusing than elucidating. -350dB is about 58 bits. In a FIR filter you need quite a lot of bits to keep from (potentially) loosing significant accuracy even at a modest number of input and output bits - for example if you have 24 bit inputs, 30 bit coefficients and you are using, say, 1024 points in your filter you’ll need 24+30+10 = 64 bits of precision in your filter or you may drop the results of small changes in your input. I have a hard time categorizing this as a -384dB noise floor, it’s really a 144dB noise floor (24 bits.) FWIW I don’t drop any bits whatsoever in the FIR filters, the art is picking the precision of coefficients that you need to keep the final output at, say, 144dB S/N. As it turns out you need more precision as you use more coefficients so you can’t really just use rules of thumb, you actually have to use tools to calculate the worst case errors for any possible inputs given your particular filter choice…
But back to your question, indeed the most significant changes between 1.2.1, Pike’s Peak and Yale was the number of bits in the coefficients and the number of coefficients. The FIR filters had all of the intermediate bits they needed to not loose any accuracy, but trading off the number of coefficients vs. the number of bits in each coefficient using did affect both the width and the depth of the soundstage (as well as the musicality IMO.)
At each place in the FPGA I used as much precision as I needed to keep a 144dB S/N path. Unfortunately I’d made a mistake in a different (IIR) filter where calculating the bits of precision needed was messier. I was using 26 extra bits of precision in that IIR filter and as it turned out using 28 instead made an audible difference in Torreys (I’d tried up to 32 extra bits in earlier releases with no noticeable change in output, but as things have gotten better over time I should have revisited some earlier choices.)
Noise in an FPGA definitely is dependent on things like the number of ground planes, the quality of the regulators you use, the quality and number of different bypass caps you use, the number of output lines that are switching at a given instant, etc. But even if all of these external factors are perfect the power rails inside any chip aren’t perfect so paying attention to which parts of the chip switch when also affects noise inside the chip… I use a six layer board for the FPGA which basically amounts to a plane for ground, a plane for the various power supplies, two signal planes for routing and I use the two outside planes as a noise shield. The problem with just adding more ground planes is that their effectiveness goes down the further away from the FPGA they are. For example, you might be better off with thicker copper in the planes you already have. Also the number of holes in the board under the FPGA affects how effective the noise control is. Making sure that there aren’t extra holes and that each hole is in the best position for the best noise control can take a while.