In his followup in the current issue, John Atkinson states that he was unable to measure any differences between Torreys and Yale (although he agreed that Torreys sounds better).
Any guesses why? Did he not measure the right things? Is it the case that in looking at the spectrum of a single tone he would not see the general lowering of the noise floor Ted has reported?
Thanks.
The point is that the changes are all below the noise floor. In particular in earlier measurements JA reports changes in resolution around -120dBFS with earlier software upgrades but still reports that the resolution is “only 17 bits” (-102dBFS). The 2nd is the noise floor and the first is resolution (the ability of the output to show small changes in the input.)
We can hear below the noise floor, JA can measure below the noise floor with long enough (or many averaged) FFTs and I don’t know why he’s so surprised that the changes from one release to the next might all be below the noise floor.
Also, FWIW there are more noise floors than just the final analog output: the internal digital algos also have noise floors and (at times) I can see them change with C++ simulations of the guts of the FPGA. There’s also self noise generated by the FPGA which is also below the analog noise floor.
More goes into the perception of more detail besides noise floor, steady state response, etc. Lowering jitter and noise generated by the FPGA adds detail, a more solid soundstage, more realism, etc. I also improved the internal accuracy of the final upsampling filter with some FPGA resources freed up by other rewrites.
I must say that I very often enjoy Ted’s posts. He gives us some amazing information and an education in the things that he does. I know and have known many engineers and the ones who can communicate clearly in plain English that mere mortals can readily understand are rare. I only know of a few who can communicate so, and they tend to be the best of their breed. Kudos Ted and thank you.
J.P.
Ted: What is the DS noise floor on digital domain? When I was reading tech discussion of another fpga based DAC, the developer stated he can here differences in sound as far as algos work at 350db noisefloor in digital domain. Especially the sense of depth gets better. Have you noticed anything similar when implementing and testing changes in algos?
Also it was stated that by implementing two ground planes (what ever that means…I am a software guy) for fpga the noise generated by fpga can be better isolated. Any opinions on that?
Talking about noise floor, especially a 350dB noise floor in digital algo’s is probably more confusing than elucidating. -350dB is about 58 bits. In a FIR filter you need quite a lot of bits to keep from (potentially) loosing significant accuracy even at a modest number of input and output bits - for example if you have 24 bit inputs, 30 bit coefficients and you are using, say, 1024 points in your filter you’ll need 24+30+10 = 64 bits of precision in your filter or you may drop the results of small changes in your input. I have a hard time categorizing this as a -384dB noise floor, it’s really a 144dB noise floor (24 bits.) FWIW I don’t drop any bits whatsoever in the FIR filters, the art is picking the precision of coefficients that you need to keep the final output at, say, 144dB S/N. As it turns out you need more precision as you use more coefficients so you can’t really just use rules of thumb, you actually have to use tools to calculate the worst case errors for any possible inputs given your particular filter choice…
But back to your question, indeed the most significant changes between 1.2.1, Pike’s Peak and Yale was the number of bits in the coefficients and the number of coefficients. The FIR filters had all of the intermediate bits they needed to not loose any accuracy, but trading off the number of coefficients vs. the number of bits in each coefficient using did affect both the width and the depth of the soundstage (as well as the musicality IMO.)
At each place in the FPGA I used as much precision as I needed to keep a 144dB S/N path. Unfortunately I’d made a mistake in a different (IIR) filter where calculating the bits of precision needed was messier. I was using 26 extra bits of precision in that IIR filter and as it turned out using 28 instead made an audible difference in Torreys (I’d tried up to 32 extra bits in earlier releases with no noticeable change in output, but as things have gotten better over time I should have revisited some earlier choices.)
Noise in an FPGA definitely is dependent on things like the number of ground planes, the quality of the regulators you use, the quality and number of different bypass caps you use, the number of output lines that are switching at a given instant, etc. But even if all of these external factors are perfect the power rails inside any chip aren’t perfect so paying attention to which parts of the chip switch when also affects noise inside the chip… I use a six layer board for the FPGA which basically amounts to a plane for ground, a plane for the various power supplies, two signal planes for routing and I use the two outside planes as a noise shield. The problem with just adding more ground planes is that their effectiveness goes down the further away from the FPGA they are. For example, you might be better off with thicker copper in the planes you already have. Also the number of holes in the board under the FPGA affects how effective the noise control is. Making sure that there aren’t extra holes and that each hole is in the best position for the best noise control can take a while.
Wow.
Just wow.
I had no clue the physical treatment of the FPGA was also so important.
Xilinx (and presumably all the FPGA vendors) have fairly specific suggestions for the minimal PCB support for their chips. Here’s one of their guides for the Spartan 6 that’s used in the DS: https://www.xilinx.com/support/documentation/user_guides/ug393.pdf
Note that these guides basically make sure you’ll get the correct behavior of the FPGA’s in question, they don’t really address how much noise and other crap you may generate 
All I can say is … 
Ted, you are the best thing about this forum… It is most educational reading your posts… You are a Polymath !
OK Ted, I think you’ll get a kick out of this:
I live outside of DC/Baltimore, my sister is “on the other coast”, and her husband is the head of R&D at one of the larger FPGA manufacturers.
A while back I was talking to my brother-in-law about the excellent, new FPGA-based DAC I had just purchased (the DirectStream). He checked out your website and reported that you used a chip from a competitor. 
As for Torreys. Especially when I listen to things like violin concertos, where a lead violinist might be a little off to the left of center, with Torreys the position of that musician in the soundstage IS better defined. One of those recordings was “live” and before Torreys I thought maybe there was a problem, as the image of the violin was not so stable. I contacted the record company, who I think contacted the artist, who said that she moves left and right as she’s playing and with Torreys, it sure sounded that way! Great job on that upgrade.
Wow. As I indicated in my previous post, Ted is a master. He is on my not too long list of people whom I would like to meet and converse with, or at least shake his hand.
Interesting story there ejr, thanks for that. These are the things that make this forum interesting to visit.
J.P.
Thanks Ted. Appreciated a lot. We hear much more low level details that measurement tools (even top ones) can show. Ted’s answers are always educative and interesting reading.
With DS dac I am using bridge 2. What I have learned that taking care of having best possible (reasonably priced) LPSs in Ethernet chain (switches, media converters) from optically isolated source (Roon server), it means lower High freq noise (EMI,RFI) injected to DS dac. In my path getting Ethernet transfer better, all I can say that now the sound of DS is much much better, natural sounding than ever (with same Torreys FW). IMHO High freq noise has a great impact on these subtle details below the noise floor. What I am trying to is that DS dac has much more “hidden” potential which can be taken into use by providing best possible data connections and power to it.