Since people have been fishing for information about the FPGA changes in the upcoming software release for the DS and DS Jr I thought I’d start a separate thread to avoid hijacking other threads.
I don’t know PS Audio’s release schedule and can’t guess because I have no idea what else they will be doing for the release.
I have sent the first potential release of the FPGA code to PS Audio: I want to see if the changes I’m doing have the desired effect. If not I’ll have to think more.
The changes are based on the things that were done for Snowmass: doing a little more shuffling of function from noisier FPGA resources to the resources I have more control over. (e.g. using distributed ram instead of the block rams.)
Also I realized that one of the things I designed in the TSS hardware can also be done in the DS Sr’s hardware. It deals with how to use the digital switches more effectively. The Jr only has one digital switch per channel so I can’t do it there.
I’d figured out how to do better filtering with the available multiply/add units in the FPGA, but I’d forgotten that the memory for filter coefficients was the actual bottleneck right now in the DS and DS Jr. I’m still looking at compressing the coefficients and other tricks to enable some other ideas I have, but I doubt they’ll make it into this release.
I have fixed the slow ramp up after a discontinuity in sample rates, transitions to and from DSD, etc.