Now comes the hard part -- Production. Maintaining DirectStream's low error budget


I took Ted’s comment in Part 2 of the video and noted that the timing and voltage errors goals he had set were one part in a million each, namely 2 microvolts and 0.177 picoseconds for each. Each would give a -120 dB error, so if a production unit saw both of these maxed out the resulting error would be the root-sum-square of the two, or 2 parts in a million, or -116.989 dB

But remember that’s not all there is in the circuit. There’s a switch and a low pass filter.

Prof. Robert Nelson showed that when surface mount capacitors are subjected to vibration they act like microphones. He characterized the resulting noise in his paper at Note that the 100 nF X7R surface mount capacitors saw a noise voltage of about 12 microvolts when subjected to random vibration of 1 g. This would totally dominate the DirectStream if it were used in the output circuit.

Fortunately I think Ted is using a film capacitor. At least I hope he is, as Prof. Nelson’s test showed a film capacitor had much lower noise when subjected to the same vibrations. The film cap had only 0.25 nano-amps of spurious current at the 1 g random vibe as compared with the surface mount cap of 2.25 nano-amps. So the film cap is clearly better by an order of magnitude.

Using a crude back-of-the-envelope calculation (OK it’s wrong, but hopefully shows the order-of-magnitude of the resulting capacitance error of 0.25 nano-amps) if I assume the capacitor is in between the driving circuit that has an output impedance of 400 ohms and the receiving circuit (in the preamp or amp) that has an input impedance of 60,000 ohms, then the 0.25 nano-amps would see an equivalent resistance of 397.35 ohms (the two impedances in parallel so the equivalent resistance is = R1*R2/(R1+R2) ) or a total error over the 60,000 ohm load of 0.0993 microvolts, or roughly one part in 10e-7.

If we RSS the previous voltage and timing errors at one part in a million each along with the capacitance error of one part in 10e-7 (assuming Ted is using a film capacitor) then the total RSS error becomes .0000014177 or -116.968 dB, or a mere blip from the -116.989 dB that we had from only the timing and voltage terms.

And I have no idea what the switch error budget is like because I don’t know the hysteresis curve of the actual switch transistor that Ted is using in the output circuit. But hopefully that error is as low as the filter capacitor and the net RSS total error is dominated by the voltage and timing terms.

So now it’s just a matter of making sure the production units have the same voltage and timing error budgets as the prototype consistently from one unit to the next.

But if there are surface mount capacitors, Nelson’s research shows there would be benefits for having a PowerBase under the DirectStream.

Isn’t it amazing that when you get to these levels of error terms that even the slightest thing that you used to ignore can dominate the error terms?



Excellent analysis, SSW. I would be curious to hear from Ted or Paul just what sort of cap is being used in the DS.


Thanks I had sent this to Paul last week but I think I made a mistake in putting the capacitor in series with the input impedance of the receiving circuit, causing all 0.25 nano-amps to go through the 60,000 ohm load. Unfortunately that was a high pass filter, not a low pass filter, so that was wrong.

Don’t know if this was any better by putting the cap in parallel with the output impedance of the driving circuit on the one side and the input impedance of the receiving circuit on the other.

Paul just ignored it, so I guess that was the right thing because that version was wrong. (I think Paul gets into ‘Ignore-it-because-there’s-no-time-to-deal-with-it-now’ mode) And that’s fine, he’s got a full plate getting DirectStream out the door and redesigning the amp for the third time.

It would be interesting to see how far off-base I am when someone looks at the actual circuits used. But the beauty of the FPGA is that one can actually look at the total error budget and defy anyone using a PCM DAC to be able to show one as simple. If used right it can be a good way to push back against the naysayers like Dr. Aix and get them to listen to it. Plus all the nerds in the audience would love it. . . .



I definitely use film caps in the audio (and final clock control filtering) for the reasons you mention. We did have some NP0/C0G’s right at the analog output connectors for EMI rejection, but as it turns out we could nuke them so we did.

I use at worst X7R MLCCs on the digital card for bypassing since microphonics there don’t really matter. I don’t feel bad about the few X7Rs in the power supply feedback on the analog card. I do have a lot of 8 legged (spider) X7R caps around for bypassing since they have a SRF at the master clock rate. On the other hand they have a much smaller reaction to bending stress or G loads than regular MLCCs.


Ted, was your production unit budget error for the voltage and timing at one part per million each, or was it set up to be 0.707 e-6 to get the total error to -120 dB?


I calculated it at 1 part per million each, but that gives a total error of -117 dB



Howdy SSW

My goal was to not stop simulating till I got the total to < 120dB, but “free” overkill was always an option. By that I mean that I also took every opportunity to get more if the cost were small enough. I used Spice to simulate everything except the code in the FPGA - for that I ran offline C++ implementations of the FPGA code and used that output to drive IBIS FPGA pin models. I didn’t use a component unless I could get a good Spice model for it. Also I used at least first order RLC models for each R, L and C. Getting some of the L’s for the C’s and visa-versa took some work, as did the transformer models. Simulating power supply events at one level and the digital circuitry running at 22+MHz at another in the same simulation took some creativity. Fortunately Spectrum Soft was very responsive to bug reports and feature requests. The Spice outputs for the power supply waveforms (both startup and steady state) as well as the DSD filtering/analog waveforms were spot on. As were the FR spectra, etc.

There was no other choice for the VCXO in that I knew that low phase noise was the key to good timing/sound and the better I could do the better the result would be. I didn’t use an error budget there. I did whatever I could think of.

The power supplies took a lot of work, they not only had to be firm, but they also needed to provide isolation one to the other and also isolation from the lines input. Verifying that the digital power wouldn’t affect the analog power any more than changes in the lines voltage, etc. took a lot of simulations/probing. And the same for all of the other combinations.




How critical was the circuitry upstream of the final switch and filter to the error budget? I’d have thought that once the data stream going to the switch was accurately timed to the 0.177 picosec and if the voltage rail on the switch output was held to the 2 microvolts, then individual errors upstream of that were moot.

Or is that an oversimplification?




Well, nothing is really irrelevant. The devil is in the details and, say, the interactions of possible resonances between the sigma-delta output and the power supplies could have been significant. The point is separating sections and simulating each section with an ideal model of other sections isn’t a very smart/comprehensive way to go. For example I needed to know that the level of bypassing around the switches was enough to keep the power supply current interactions within the bandwidth of the power supply regulators. I used stepped simulations with various combinations of bulk and HF bypassing to see where the tradeoffs were and, for example, how many bypass caps did I need to keep the THD down to acceptable levels. (I couldn’t squelch the THD, but I could see where more power supply work wouldn’t help.)

I did forgo simulating the digital input card’s inputs in the analog output simulations. I just went from the FPGA on out to the output there. I used separate simulations to verify the isolation of the digital inputs from the clock and analog output supplies over frequency…

I really did need to see if line input changes or digital input noise could go back thru the digital supplies and thru the clock supplies and affect jitter…

I could have done all of this at a higher level, but the chance of missing something was too great. There’s nothing like simulating the very schematics the boards are built from.


My heart is smiling! :x


Ted thanks for explaining all that you did. It really shows just how much it all matters. So vibration eliminator a matter now that is something I never did think made any sense.



Hi Ted,

I’m kinda of curious. I understand that things do get built to a price point more or less… So if you had zero price constraints what do you think you would change? How much cost would it add? And do you think it would substantially effect and improve the unit?

I’m mean things like dual mono fully regulated outboard power supplies… Mundorf caps, .5% Nude Vishay’s, WBT jacks…

Please understand I’m NOT saying you guys cheeped out, I’m just asking if you had money to throw at it what kinds of area’s would you look at?

erikm said Hi Ted,

I’m kinda of curious. I understand that things do get built to a price point more or less… So if you had zero price constraints what do you think you would change? How much cost would it add? And do you think it would substantially effect and improve the unit?

I’m mean things like dual mono fully regulated outboard power supplies… Mundorf caps, .5% Nude Vishay’s, WBT jacks…

Please understand I’m NOT saying you guys cheeped out, I’m just asking if you had money to throw at it what kinds of area’s would you look at?

Tho we had a tight budget I was pleased that I didn't feel I had to compromise on any given component. We learned enough from my previous boards to better my monster prototype with these much lower cost boards. We've learned some more here too.

If development time were free, I’d make more test boards to see if there are any non-intuitive part substitutions that sound better.

6 channels?

I’d probably use the Jensen JT-11SSP-6M or JT-11SSP-8MA (which I don’t see at their site anymore?) Or perhaps I could talk them into a “worse” transformer that meets our needs better.

A separate power supply case with separate transformers for each of the umpteen power supplies, another layer of regulation in the power supply box as well as the DAC box.

Bigger FPGA, just to have expansion and upgrade room.

Tho manufacturing could be a pain, thicker boards with thicker copper - I don’t see a need for Teflon or other esoteric board materials

More raw space between digital and analog

Since everything is surface mount there are fewer “audiophile” component available, but we’re already a long way toward nude Vishay’s etc. by using quality components. I’d still try to upgrade them anyways.

There are a few items that we could seriously upgrade with slight changes to the architecture.


Interesting…Thanks Ted…