Hi @tedsmith. As a music lover, I’m thoroughly enjoying your creation and spending way too much time in the sweet spot when there are other things I ought to be doing. As a geek, I’m fascinated by how you managed it. Hoping you’ll be able to shed a little more light on how exactly the data coming from external sources gets loaded into the FPGA for processing.
In particular I’m curious about the significance of the “170MHz Input Processing” described on the product website (which I suspect is a rounded-up 169.344MHz?) and exactly how and where the 32-bit subframes of SPDIF data become 24-bit samples. Is it simply that the FGPA is sampling a serial data stream at ~170MHz such that it has at least three cycles to detect each of the bi-phase mark transitions for stereo SPDIF data with a 352.8kHz sample rate? Or do you have external SPDIF decoding and then I2S lines coming into the FPGA?
And how does “native” DSD over I2S fit into this?
I understand that some things have to remain confidential for commercial reasons, and apologies if I’ve missed where this is already explained elsewhere, but whatever you can share would be appreciated.