Indeed it is 169.344MHz, tho I’ve used plenty of other similar rates.
I don’t attempt to recover the incoming clocks from I2S, S/PDIF, AES/EBU, TOSLink, etc. Instead I sample all incoming digital inputs at the 169.344MHz rate and look for patterns in the bits. For I2S it’s pretty simple - I watch for the first high clock after a low clock and then I use the corresponding LR clock and the Data samples. For raw DSD over the HDMI connectors I use the left and right samples when I first see a high clock.
The Bi-Phase Mark encoded signals are decoded by noticing whether a transition is missing compared to the recent history of the signal.
The whole point is to not be held hostage by the jitter, bugs and sample rate restrictions that exist in S/PDIF receiver chips, etc.
It’s quite simple: the more accurately you track an incoming clock the more of it’s jitter you are letting thru, so I ignore the timing of their edges entirely.