As I obliquely implied above the noise and jitter generated in the FPGA was a major source of work in the DS’s FPGA software. The Xilinx FPGA tools keep track of jitter at every point in the FPGA, but the goal of the routing software is to keep that jitter from becoming large enough to disrupt the logic function. But short of that the software doesn’t try to minimize jitter. The FPGA hardware has separate routing networks for clock like signals to keep jitter, skew and other potential corruptions to a minimum. Most FPGAs provide something akin to PLLs to generate clocks based on other clocks. The output clocks may need to be phase aligned with the PLL input clock (or not.) The PLL can be configured to minimize the effects of input jitter, to minimize the output jitter or some compromise in the middle. (I’m getting side tracked.)
The FPGA software also has to worry about noise generation. One major source of noise is when signals make a transition: the more nodes a network drives the bigger the effects a transition has on the power supply: not only potentially lowering the voltage in a local are of the FPGA, but also potentially raising the ground level in a local area. The clocks are usually the biggest networks and generate a lot of noise on each transition. The Spartan 6 that the DS used had DCMs (Digital Clock Manager) which were like PLLs. One of the features of those modules was that for any input clock they would provide four outputs of that clock at 0, 90, 180 and 270 degree offsets. It turns out that each of these has differing jitter and noise so one trick I used in the DS’s FPGA code was to use phase 3 (270 degrees) for critical work since that had the smallest amount of jitter. Each trick like this made an audible difference in a software release.
The DS tried to keep noise on the FPGA down by using more bypassing than the minimum recommendations, by careful routing of clock signals and other FPGA inputs and outputs and by reclocking on the analog board to try and keep the rest of the analog board from reacting to noise from the digital board.
A few of the problems with the DS related to the above were:
- When I was routing the FPGA on the DS I accidentally didn’t separate the power and ground of the power supply for the PLLs from the power supplies for the FPGA inputs and outputs. I was annoyed with myself because I’d carefully separated them on my original prototype and on the DS Jr. So this meant that transitions on the FPGAs input and outputs would cause more jitter and noise for the internal FPGA clocks than they needed to. If we ever had to turn the boards on the DS that would have been one additional thing I’d have fixed.
- Noise from the switching inside FPGA also polluted the system’s overall 3.3V and 5V power on the digital card. I used a lot of bypassing but, bypassing can’t clean up everything. In an ideal world that noise on the 5V supplies wouldn’t have affected the analog board’s 12V supply, but there are always effects. The DS modders know what a difference using a completely separate power supply for the analog board makes.
So what’s different in the Mk II related to these things?
The newer FPGA used in the Mk II keeps noise down internally a lot more than the older FPGAs in the DS. They have a different architecture for clocking and new different PLL implementations. You can get more done in each cell of the new FPGA so there are fewer connections between cells so (assuming the same complexity of FPGA code) there’s less noise generated by signals connecting cells together.
The Mk II has two reclockers in series, this should filter out more noise from upstream.
The Mk II has power supplies for the digital and analog cards that are more separated from each other and they also regulate their voltages better. This helps to isolation interactions between the cards thru the power supplies.
The FPGA PLLs in the Mk II have their own power islands 
In the Mk II FPGA I’m using an entirely separate clocking network just for clocking the DSD outputs. Its phase is adjusted to transition when no other clocks in the FPGA are transitioning. The big change in the Sunlight release of the DS from previous DS software releases was taking a step in this direction so we know that it matters.
The Mk II has more bypassing around the FPGA and higher capacity regulators for the three different voltages that the FPGAs need.
The isolation between the FPGA and the analog card’s reclocker on the DS was done by capacitors. On the Mk II we are using explicit digital isolation chips with the FPGA facing side powered from the digital card and the reclocker facing side powered from the analog card. There are three isolators, one for the clock from the analog card to the FPGA, one for the differential DSD signals from the FPGA and one for the control signals from the control processor on the digital card to control things like the configuration relays and the VCXO rate.
The ribbon cable from the FPGA to the analog card is a more expensive better-quality cable than the one in the DS. It should introduce less jitter and shield the DSD signals from more noise than the one in the DS. It also doesn’t physically go over components on the analog card.
You can get an idea of the cable’s size by comparing it to the screw in the bottom left of the image.
All in all the biggest sources of noise from the FPGA have been eliminated or at least remediated.