Already moved. See above. 
You have to buy your own HDD, anywhere from 2TB to 8TB.
Hey Ted,
Enrico from Tuscany Italy here. Any news on when your Signature DAC will be available for purchase? I havenāt heard anything about it for a while now and wanted to make sure the project was still going forward. Thanks for your answer.
Cheers,
Enrico
The TSS was interrupted for the DS Mk II, which, in turn was delayed by the global parts supply disruptions. The TSS is still on the schedule, but guessing the time frame is impossible.
A post was merged into an existing topic: Wishes Upcoming PSA DirectStream MKII
Hey Ted. New to the forum but long time admirer. I have 3 PS Audio Products at the moment. Iād like to private message you but donāt know how to do so. Could you PM me and then I can reply sonI can get the hang of it. I wish to purchase the TSS DAC and if possible be a beta tester. Iād like to pay or leave a deposit to be first on that list, but I digress. I have a few questions and would love to pick your brain if you wouldnāt mind. Thanks for all your genius commentary here and on YouTube.
Cheers,
Enrico
Hi there just to let you know the TSS is not completed and there is no current schedule when it will be released. The DirectStream Mk 2 is the next new DAC and it should be available withing a few months.
The Mk2 was designed based on the TSS albeit a cost reduced model. Itt was estimated the TSS would sell for around $15K the Mk2 is estimated to sell for about $7K.
Hope that helps
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Yeah man it does. Thanks.
I would like to beta test the MKii if possible. How donI get on that list?
Itās unlikely if you are outside the US or Canada.
Boo to that
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Happy Cake Day!
I am sure those slots filled up a long time ago we started the list back in June. The will probably only do about 20 beta units and they probably have 200 takers 
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Thanks Elk, Itās been a great few years. I have a another cake day in a few weeks.
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Hi @tedsmith
Where are things with the TSS?
Looking for release is 1st half of this year or 2nd half?
Any global component shortages affecting things?
Is TSS coming out before or after DS DAC Mk2?
Hasnāt been an update here for quite a while so I thought Iād ask 
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Iām actively working on it now. Iāve replaced many components with ones Iām hoping will continue to be available for a while. Iām essentially done with the schematics, I have to relayout most everything, but since PS Audio is now doing a different chassis design Iād have to wait for the final routing anyway (but Iām making some guesses )
I canāt predict the release time. PS Audio is still committed to releasing it, but between parts issues and trying to work with more realistic schedules I donāt have much hard data.
Most of the āpopcornā parts needed to be replaced and many others too.
The DS Mk II is definitely going to come out first. Weāre waiting for boards and completion/testing of the UI software. Barring sound quality issues I donāt expect to have to do much more work on the FPGA.
Some random TSS updates:
Weāll probably be using three FPGAs, and we have them in stock. (I usually save fixing up the silkscreen text till near the end so forgive the jumble):
The optical link will have twice the bandwidth that we expected. This will be more useful later but now it will contribute reliability.
Related to that: I rewrote the FPGA code that synchronizes and communicates to the analog box. Now it will keep the FPGAās clock phase synchronized within 20 or so picoseconds of the analogās upcoming clock phase (it doesnāt need to be this precise, but itās a real number.) Itās similar to a digitally controlled PLL: I use multiple inputs to calculate an advance or delay for the local clock to keep near to the synchronization signal from the analog box (not a clock edge). It syncs up much faster than the old code/boards and Iāve done a lot of testing to make sure it works no matter what state the boxes come up (or how long the optical cable is.)
Iāll be taking advantage of some of the extra FPGA horsepower in the first release, but Iām not sure exactly what Iāll be doing yet. Iām running simulations of some of my ideas.
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Care to expand on this? Whatās the purpose? Is this the connection between the two boxes?
Thanks!
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I always enjoy your updates, Ted. Hope you donāt mind me checking that Iāve understood you correctlyā¦
The analog box is not as analog as say a class AB amplifier or a crystal radio set, but does basically no arithmetic beyond add/subtract for local state management if that. Its local clock drives the whole operation, which includes sending out a synchronisation pulse to the digital box and watching for bursts of binary data in time with that pulse. The binary data includes control parameters for relays that set output level and ground lift, packets of DSD bits, and a signal that can increase or decrease the local clock rate to pull it into alignment with the flow of audio data from whatever transport is currently being listened to.
So on initial power on or after reconnect of the optical cables, the digital box has to watch the sync pulses to know how fast the analog box is currently running, and once itās locked on to that it can send correctly-timed bursts of audio and instructions down the other fibre.
Am I close?
Ted, any hint on the new chassis discussions? Will separate chassis stay or will it be combined in one unit but shielded?
[In reference to the optical link:]
Still two separate boxes with an optical link between them. They are mostly revisiting the shape of the boxes. I saw one rendering that didnāt look bad. But theyāve moved on from that.
Pretty close. Iāll reword things to possibly give a more detailed idea about whatās going on.
The analog box has the master clock which is physically very close to the final reclocker, but there are three other things running off of it: another (earlier) reclocker, a deserializer and the optical link to the digital box.
The deserializer is the most digital thing in the analog box. Itās takes the serial bitstream from the optical receiver and converts them to parallel output chunks. These chunks have four bits of DSD (a differential bit for each of the left and right channels) and some control stuff (described below). The DSD bits go directly into the reclockers and since the digital box is synchronized to the analog box these bits are ājust in timeā: their phase is well controlled and wonāt slip relative to the reclockers.
How?
The clock that goes up to the digital box over the optical link has four serial bits per frame. One one bit followed by a data bit followed by the sync followed by a zero bit. Since thereās always a zero bit followed by a one bit every four clock times the digital box can align with the upcoming signal.
The sync bit is actually a direct sample of the first bit of each chunk in the down coming bit stream (no logic required.) The digital box can look at this return bit to see that itās as random as possible which ironically means things are synced up. (If the bits are all the same the digital box knows itās either too early or too late, i.e. a run of zeros means itās early and needs to slow down its local clock and a run of ones means it needs to speed it up.) Each zero or one tells the digital box to speed up or slow down the local clock by 13 picoseconds per clock tick. (For each clock tick thatās about 1 out of 6720 steps of phase shift.)
The control bits that also came down in each chunk are an SPI signal.
Serial Peripheral Interface - Wikipedia
Basically a (much slower) clock and data bit that are a standard communication protocol used to talk between microprocessors and various peripherals. These peripherals in the analog box include:
- the DAC/potentiometer which controls the VCXOās clock rate,
- the embedded measuring ADC that samples things like the voltage levels, temperature, etc. in the analog box, and
- The control of the relays for ground lifts and the output configuration.
E.g. The SPI tells the measuring ADC what to measure and when to send its result to the digital box. The return SPI data bit is the data bit in the upgoing optical frames.
All-in-all the non-analog parts of the analog box are the deserializer chip, the potentiometer chip that sets the VCXOās frequency and the measuring ADC chip. These each have their own power supplies coming from a separate power transformer in the analog box than the power transformer that provides the analog power.
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Could you go a little deeper on the format of the āchunkā or its framing please to help me understand why the first sampled bit would be a zero if the digital box is running ahead and a one if the digital box is falling behind?
Iām guessing youāre not using a bi-phase-mark scheme for your bit representation because thatās inherently a clock signal? So you would have ālightā equals a 1 and ādarkā equals 0 or vice versa?
I could imagine a chunk starting with one or more 1 bits, the detection of which provides feedback that the transmission is arriving later than is ideal. Followed by one or more zero bits to provide a point of demarcation. It sounds like the feedback scheme works to try and keep the first sample by the analog box aligned at that transition from 1 to 0. Is the deserialization directly triggered by a following 0-to-1 transition?
Given the DAC output rate is either 2x or 4xDSD (Iām not sure where youāve landed) we must be talking about an optical switching rate in the tens to low hundreds of megahertz?
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